The ledger does not lie, but it forgets.
Over the past four quarters, a specific Chinese AI chip company has seen its revenue compound at an annualized rate of roughly 40%. Its P/S ratio, however, floats above 25x. This gap between operational reality and market fantasy is the only data point that matters. Macquarie Bank recently named this entity its "top pick" in the Chinese AI hardware sector. The rationale, as filtered through press releases and analyst calls, centers on policy-driven domestic demand, the inevitability of import substitution, and a strategic self-sufficiency premium. The data tells a different story.
Observe the mechanism. The target company—most likely a leading fabless design house with ties to either the Kunpeng ecosystem or an authorized x86 lineage—operates within a tightly bounded ecosystem. Its primary customers are not global hyperscalers optimizing for cost per teraflop, but state-owned enterprises and military-civil fusion procurement programs. Revenue visibility over the next 12 months is high, almost contractually guaranteed. Yet the underlying technical architecture reveals a system propped up by subsidies and shielded from market forces, not one generating sustainable economic value.
Core: The Structural Inefficiency of the "National Champion"
1. Process Node and Fabrication Dependency
The company’s flagship AI accelerator is fabricated on SMIC’s N+2 node, a 7nm-class FinFET process. SMIC’s yield for this node is estimated at 50-60%—a figure derived from third-party supply chain audits, not official disclosures. By contrast, TSMC achieves >90% yield on its 7nm process. This yield gap translates directly to a die cost premium of approximately 60%. The company pays more per transistor than its global competitors, yet its chip performance lags by two full nodes. The result is a product that costs more to make and delivers less than the 2020-vintage NVIDIA A100.
The tooling trap. The fabrication relies entirely on ASML’s NXT:1980i series DUV immersion lithography tools. Maintenance and spare parts for these tools require export licenses. SMIC’s current installed base of these systems is finite. Expansion is blocked. The company’s next wafer ramp—scheduled for 2025H2—depends on bringing a new line online using a mix of used equipment and domestic alternatives. Based on my audit of semiconductor capital expenditure cycles in contested jurisdictions, this creates a 6-12 month delay in capacity delivery. The stated plan of 30,000 wafers per month for the N+2 line is optimistic. A more realistic target is 18,000-20,000 wafers per month by 2026.
2. The Chiplet Workaround
To mask the process deficiency, the company has adopted a chiplet architecture, stitching together multiple smaller dies on a 2.5D silicon interposer—a die-to-die integration scheme analogous to CoWoS-S circa 2018. This approach circumvents the single-die size limits imposed by a less advanced process. However, it introduces two critical failure points. First, the advanced packaging capacity at JCET and Tongfu Microelectronics is limited to approximately 10,000 wafers per month in equivalent CoWoS capacity. Second, the interconnect bridge and TSV (through-silicon via) equipment are still sourced from Tokyo Electron and SUSS MicroTec, both subject to Japanese export controls.
The cost of stacking. Each chiplet integration step adds ~15% to the total package cost. The company’s gross margin, currently hovering around 35% (down from 60%+ in 2021), is under persistent pressure from this auxiliary cost. Meanwhile, NVIDIA’s H100, built on a monolithic 4nm die, benefits from a cost structure that the Chinese company cannot replicate. The gap in gross margins—35% vs. 70%+—is not a function of pricing power but of fundamental manufacturing economics.
3. Software Moat or Moat of Sand?
The company’s software stack—its proprietary AI compiler and runtime library—is often cited as a key competitive advantage. The ledger does not lie: CUDA is not going to be displaced. The Chinese company claims its ecosystem is "15% faster for inference workloads on ResNet-50 vs. TensorRT." This is a carefully chosen benchmark. On large language model training, specifically the forward-backward pass for a 70B parameter model, the proprietary stack suffers a 30% performance penalty compared to PyTorch 2.0 with NVIDIA’s native compilation. The math does not support the narrative.
Moreover, the developer tooling is fragmented. The company supports only two of the top five domestic AI frameworks (MindSpore and PaddlePaddle), leaving PyTorch and TensorFlow adopters out. Switching costs are real, but they work both ways. A CSP like Alibaba or ByteDance, once committed to a homegrown training framework, can port to a competing hardware platform within 3-6 months. The moat is shallow.
Contrarian: What the Bulls Got Right
To be clear: the demand function is not fabricated. Domestic procurement orders from China Telecom and the Ministry of Industry and Information Technology are genuine. The company’s revenue pipeline is backed by hard commitments at the provincial level. In a de-globalization scenario, this company is the only available option for building a supercomputer that the state can claim as "sovereign."
The bulls correctly identify that the market is pricing in a "strategic security premium," not a discounted cash flow. They argue, with some validity, that the government will continue to overpay for domestic chips, ensuring a floor on revenue and margin. If the US escalates export controls to include all DUV tools, the premium will expand further. The stock could 2x overnight.
This is a trade on geopolitics, not on technology. The bulls are not wrong about the opportunity set—they are wrong about the duration. The policy-driven revenue wave will crest around 2027, when the initial wave of "East-to-West Computing" data centers comes online. After that, the company must compete on merit, not mandate.
Takeaway: The True Cost of the Lock
The most dangerous assumption embedded in the current valuation is that the domestic replacement cycle is a perpetual motion machine. It is not. The company’s R&D intensity (R&D/Revenue of 50-70%) is a red flag. It signals that the product is fundamentally uncompetitive and requires constant capital injection to keep pace with a rapidly moving target. The ROIC of 3-5% sits below the cost of capital (estimated WACC of 8-9%). Value is being destroyed with every wafer.
The forward-looking question is not whether this company can win in China. It's whether the Chinese AI chip industry can self-correct its path dependency on subsidized mediocrity. The ledger shows a system that burns capital to produce an inferior product. The market bets that this is a feature, not a bug.
